By Stephen Nellis

(Reuters). – Researchers at Intel Corp (NASDAQ) On Saturday, the company revealed work they believe will enable it to keep shrinking and speeding down computing chips for the next 10 years. This includes several technologies that allow the stacking of parts of different chips.

Intel’s Research Components Group presented the results in papers during an international conference held in San Francisco. This Silicon Valley firm is trying to regain its lead in the production of small and fast chips, which it lost to competitors like Samsung Electronics (OTC) Co Ltd.

Pat Gelsinger, Intel CEO has laid out plans for regaining the lead by 2025. However, Saturday’s research gives insight into Intel’s plans beyond 2025.

Intel’s strategy to pack more computing power in chips is by stacking “tiles” (or “chiplets”) in three dimensions, rather than producing chips as one piece of two-dimension. Intel presented work on Saturday showing that it could enable 10x the number of connections between tiles. That means more tiles can be placed on top.

Perhaps the greatest advance Saturday was a paper that showed how transistors can be stack. This tiny switch, representing 1s and 0, represents digital logic. It forms the basic building block of chips.

Intel claims that the new technology can increase the amount of transistors within a single chip by 30% to 50%. Chips have been getting faster for 50 years because they are packing more transistors.

Paul Fischer (director and senior principal engineer at Intel’s Components Search Group) told Reuters, “By stacking them directly on top, we’re clearly saving space.” We are reducing the length of interconnects, and actually saving energy. This makes it not only cheaper but also more efficient.